1) Field of the Invention
The present invention relates to an I/O interface control suitable for data processing equipment that constitutes a computing system and that is connected to an I/O unit such as a direct access storage device (DASD). Specifically, the present invention relates to an I/O interface control method that can deal more effectively with an abnormal state (check/stop) in a channel control unit arranged within data processing equipment to be connected to an I/O unit. The present invention also relates to data processing equipment that can deal more effectively with an abnormal state (check/stop) in a channel control device arranged within the data processing equipment to be connected to an I/O unit.
2) Description of the Related Art
The general entire configuration of data processing equipment at which an I/O unit such as a DASD is connected is shown in FIG. 7. Referring to FIG. 7, the data processing equipment 1 includes a central processing unit (CPU) 10, a main storage unit (MSU) 11, a main storage control unit (MCU) 12, an input/output processor (IOP) 13, and a channel element (CHE) 14.
Plural I/O units 15 such as DASDs are connected to the data processing equipment 1 via the I/O control unit 16, respectively. As shown in FIG. 7, plural I/O control units 16 are connected to the plural I/O units 15, respectively.
The CPU 10 executes various processes based on data stored in the main storage unit 11. The main storage control unit 12 controls data flow between the main storage unit 11 and the CPU 10.
The I/O processor 13 is connected to the main storage unit 11 via the main storage control unit 12 to control a data flow between the I/O unit 15 such as a DASD acting as peripheral equipment and the main storage unit 11 by way of the channel element 14 and the I/O control unit 16.
As shown in FIG. 8, the I/O processor 13 is formed of the channel control unit 13A and the transfer control unit 13B.
The channel control unit 13A controls respective channel elements 14. The transfer control unit 13B controls data to be transferred between the main storage control unit 12 and the respective I/O unit 15.
Each channel element 14 acts as a functional unit that performs a data transmission between the main storage control unit 12 and each I/O units 15. Each channel element 14 receives data from the main storage unit 12 to be transferred by the transfer control unit 13B to a specific I/O unit 15 via the I/O control unit 16.
In FIG. 8, the CPU 10, the main storage unit 11, and the I/O control unit 16 are not illustrated, but one channel element 14 as well as one I/O unit 15 are illustrated. As shown in FIG. 8, the channel element 13A includes a check/stop signal producing circuit 17 (to be described later).
Generally, the word "check/stop" means that when an emergent serious trouble occurs in the data processing equipment shown in FIGS. 7 and 8, the related circuitry at the accidental spot is halted.
For example, when the channel control unit 13A in the data processing equipment 1 becomes a check/stop state due to a hardware failure, the I/O interface cannot continue its sequence operation so that the I/O unit 15 is hanged up. As a result, the trouble may affect the operation of other data equipment sharing the I/O unit 14. Hence, if a check/stop should occur in the channel control unit 13A, the I/O interface should be released quickly.
In the conventional data processing equipment, shown in FIG. 8, the channel control unit 13A includes the check/stop signal producing circuit 17. When the channel control unit 13A becomes a check/stop state, the check/stop signal producing circuit 17 outputs a check/stop signal to the main storage control unit 12 and the channel element 14 to notify them of the abnormal state of the channel control unit 13A.
When the channel element 14 receives the check/stop signal from the check/stop signal producing circuit 17,.it outputs immediately a selective reset signal, thus releasing the I/O interface from the I/O unit 15.
The main storage unit 12 receives a check/stop signal from the check/stop signal producing circuit 17, it separates quickly the channel control unit 13A while it interrupts the data transfer during a data transmission (or performs interface cutting process) since the main storage unit is released under software.
As described above, according to the prior art, when it receives a check/stop signal informing an abnormal state of the channel control unit 13A, the channel element 14 issues immediately the selective reset signal to release the I/O interface. Hence when the check/stop occurs during a data writing to the I/O unit 15 such as a DASD, the block (or record) during the writing operation, as shown in FIG. 9, is padded zero after the check/stop occurrence, whereby an improper data block is written to the I/O unit 15.
Similarly, since the main storage control unit 12 separates immediately the channel control unit 13A in response to the check/stop signal from the channel control unit 13A and interrupts the data transmission, even if the channel element 14 does not issue the selective reset signal, the transfer operation results in an overrun of data or zero-padding is carried out to the block during a writing operation. It has been very difficult to recover the software if there should be a block which is zero-padded or broken.